1) Field of the Invention
The present invention relates to communications networks in general and in particular to apparatus and techniques used to interconnect components within devices coupled to said communications networks.
2) Prior Art
The proliferation of communications devices has created the need for uniform standards to which a manufacturer is obliged to observe in order to interconnect one manufacturer""s equipment to the equipment of another manufacturer. The standards are, usually, not mandatory. But a manufacturer whose equipment does not comply with an adopted standard may not be able to communicate with equipment from other manufacturers. As a consequence, the sale of equipment from the non-complying manufacturer may be less than it would have been if he had complied.
As a consequence it is common industry practice for manufacturers to form working groups which promulgate standards pertaining to a particular technology. The Optical Internetworking Forum (OIF) is one of such working group which promulgates standards for OC-192 System Interface for Physical and Link Layer Devices. The interface is often referred to as the SPI-4 interface which interconnects Physical Layer (PHY) devices to Link Layer devices for 10 Gbps for aggregate bandwidth applications. Details of the SPI-4 interface is set forth in the OIF document titled: xe2x80x9cSystem Packet Interface Level 4 (SPI-4) Phase 2: OC-192 System Interface for Physical and Link Devicesxe2x80x9d or its successor documents which can be obtained from Optical Internetworking Forum, 39355 California Street, Suite 307, Fremont, Calif. 94538 or successor organization and is incorporated herein by reference.
In order to set the background against which the present invention was developed portions of the SPI-4 Interface standard are described with reference to FIG. 1. The SPI-4 interface 10 is a Point-to-Point interface coupling PHY Device 12 to Link Layer Device 14. The Link Layer Device 14 includes Transmit Link Layer and Receiver Link Layer Device. The SPI-4 Interface 10 includes transmitting data clock (TDCLK), transmit data (TDAT) and transmit control (TCTL). The named signals are from the Transmit Link Layer Device to PHY Device 12. Likewise, SPI-4 Interface 10 includes receive data clock (RDCLK), receive data (RDAT) and receive control (RCTL) from PHY Device 12 to the Receive Link Layer Device. Associated with the RDCLK, RDAT and RCTL are RSTAT and RSCLK. RSTAT is a 2-bit channel transmitting status information from Receive Link Device to PHY Device 12. Clock signal associated with the 2-bit channels is transported on RSCLK. A 2-bit channel labelled TSTAT and clock line labelled TSCLK associated with TDCLK, TDAT and TCTL, carries status information from PHY Device 12 to Transmit Link Layer Device. The arrows in FIG. 1 indicate the direction in which information flows.
The RSTAT channel, RSCLK, TSTAT and TSCLK relate to the present invention set forth herein below. As a consequence further discussion will be limited thereto. Except for flow direction, the characteristics and functions of TSCLK, TSTAT and RSTAT, RSCLK are identical. Therefore, only one set will be described with the understanding that the description relates to both pairs.
As defined in the standard the Status Channel (TSTAT or RSTAT) is a 2-bit digital channel with four unique bit patterns 00, 01, 10 and 11. The bit pattern xe2x80x9811xe2x80x99 is the synchronization character and cannot be used to transmit useful information. In fact, only three bit patterns 00, 01, and 10 are available to transfer useful information. However, there are several situations requiring more than 3 (three) 2-bits independent bit pattern to transmit more complex information on the two bit status channels. As a consequence, there is a need to provide more independent bit patterns on the two bit status channel without altering its characteristics such as changing the xe2x80x9811xe2x80x99 synchronizing bit pattern.
In addition, there are times when increased bandwidth is required to transmit information on the status channel.
The present invention increases the bandwidth on the status channel by providing a scalable interface including n 2-bit channels, n greater than 1. The information to be transmitted is distributed over the n channels. The increase in bandwidth is achieved without changing the clocking set forth in the above-identified document or xe2x80x9811xe2x80x99 synchronization bit pattern. The bit pattern is increased by using a 3b/4b coding and not using predetermined bit patterns with xe2x80x9811xe2x80x99, located in certain positions of the patterns, to transmit data.
In particular a digital stream of data to be transmitted on the n 2-bit channels is partitioned into groups of 3 bits which are encoded into 4 bits and each pair of the 4 bits is forwarded onto different 2-bit channels using the same or back-to-back clock cycles. Selected bit patterns with adjoining xe2x80x9811xe2x80x99 are discarded and not used to transmit information on the 2-bit channel. Contiguous clock cycles are used to gate pairs of the coded 4 bits onto different 2-bit channels.
The efficiency is further enhanced by using a clock cycle to gate the xe2x80x9c11xe2x80x9d framing pattern onto one of the 2-bit channels and the first 4-bit pattern, in a set of 4-bit patterns, to be transmitted is distributed and gated by the same clock cycle over other 2-channels in the interface. Thereafter, the other 4-bit patterns in the set of patterns to be transmitted are distributed over the channels of the interface in a round robin manner, with the 2-bit channels in the interface operating simultaneously.